Digitronics Corp. v. New York Racing Ass'n, Inc.

Decision Date04 April 1977
Docket NumberNos. 338,D,339,s. 338
Citation193 USPQ 577,553 F.2d 740
PartiesDIGITRONICS CORP., now Amperex Electronic Corp., Plaintiff-Appellant-Cross- Appellee, v. The NEW YORK RACING ASSOCIATION, INC., et al., Defendants-Appellees-Cross- Appellants. ockets 76-7063, 76-7085.
CourtU.S. Court of Appeals — Second Circuit

S. C. Yuter, New York City (Daniel M. Rosen, Wallace E. J. Collins and Yuter & Rosen, New York City, of counsel), for plaintiff-appellant-cross-appellee.

Robert E. Isner, New York City (Charles N. J. Ruggiero, Arthur A. March and Nims, Howes, Collison & Isner, New York City, of counsel), for defendants-appellees-cross-appellants.

Charles W. Sims, Dayton, Ohio, and Francis N. Carten, Stamford, Conn., on brief for Digital Systems Corp., amicus curiae.

Before MOORE, OAKES and TIMBERS, Circuit Judges.

OAKES, Circuit Judge:

This appeal involves a patent issued for a data processing system that, when used in place of the prior art in parimutuel wagering equipment, is said to produce speedier, more accurate and more versatile paraphernalia for the placing of wagers at race tracks by those interested in the ancient and honorable art of improvement of the breed. The United States District Court for the Eastern District of New York, John F. Dooling, Jr., Judge, in a 216-page opinion with 52 formal findings and conclusions, supplemented by explanatory appendices, held the patent invalid for obviousness under 35 U.S.C. § 103. 1 He also held that appellees' counterclaim for attorney fees could not be sustained, since the case was not sufficiently "exceptional" to permit the discretionary award of attorney fees under 35 U.S.C. § 285. Part of the extensive opinion has been published at 187 U.S.P.Q. 602 (E.D.N.Y.1975). On both the appeal from the judgment of invalidity and the cross-appeal from the denial of the counterclaim for attorney fees, we affirm the judgment.

I.

This action was brought by appellant's predecessor, Digitronics Corp., which sought an injunction and damages from the New York Racing Association, Inc., Automatic Totalisators (U.S.A.) Ltd. (ATUSA), Automatic Totalisators Ltd. (Amtote), and Premier Equipment Proprietary Ltd., for alleged infringement of U. S. Patent No. 3,252,149, issued on May 17, 1966, to Digitronics as assignee of five named inventors. The invention, according to papers filed with the Patent Office, "pertains to data processing systems and more particularly to systems for processing data received from ticket issuing machines," one of the most common of which is "a parimutuel system employed for servicing transactions or wagers made by spectators at sporting events." The patent contains 33 claims, but only claims 20-27 are in issue here. A considerable portion of Judge Dooling's opinion is devoted to developing for the reader a reasonably simplified, albeit unavoidably difficult to follow, primer of knowledge regarding the data processing circuitry and "logic" here involved, including, inter alia, explanations of the meaning and operation of the components used. 2 The patent itself frequently refers to R. K. Richards, Arthmetic Operations in Digital Computers (1955), which discloses many of the fundamentals of computer logic applicable in the field of data processing generally.

The patent is entitled a patent on a "Data Processing System," and each of the claims in question is one for a "system comprising" a plurality of ticket issuing machines (TIMs) or a TIM followed by a combination of particular means. As Judge Dooling found, the system is primarily an aggregator system, aggregating the number of wagers placed on each entry in two separate aggregators: the central memory register, which aggregates the wagers on each horse in each of the pools, and the TIM aggregator, where the number of wagers at that particular TIM on each horse in each of the pools is similarly (and simultaneously) aggregated. These are updated by a "unit adder" every time an additional wager is registered by any TIM. The computer draws from the central memory register the total wagers in each of the three pools and on each horse in the pool and uses those sums to compute the odds on each entry and to feed to the output display boards the results of the odds changes every 70 seconds. While elaborate circuitry is required to accomplish this, the circuitry itself is unimportant for our purposes; Judge Dooling's finding, that "there is no novel circuitry involved as is clear from the face of the patent and from the trial evidence," is not disputed here.

Appellant characterized below the subject of Claims 20 through 22 as the "totalisator system" invention, Claim 23 as the "nonallowed runner subsystem" invention, Claims 24 and 25 as the "TIM scanning subsystem" invention, and Claims 26 and 27 as the "erroneous data subsystem" invention. Claim 20 consists of the combination of a plurality of conventional TIMs, means of collecting from them and dispatching into the system the betting data on each entry and identifying those data to the original TIM, and means of aggregating the wagering data and sending an acknowledgment signal to the TIM so that it will stamp up and issue a ticket to the bettor with the wagering data on it. The system is composed of a set of commercially available, fairly standardized TIMs, an electronic linkage between them, an aggregator, a unit adder, and an "acknowledgment signal amplifier" between the unit adder and the TIM so that aggregating the wager effects an electromechanical release of the betting ticket. The purpose of the system is to aggregate wagers without losing track of the horse on which and the pool in which the wager was placed or the TIM at which the wager was placed. Judge Dooling found that each component was common in the prior art, existing in various forms, and performed its familiar role in a familiar way, all as basically described in Richards, Arthmetic Operations in Digital Computers, supra.

As to Claim 21, the court found that it added nothing to the combination, merely particularizing Claim 20, 187 U.S.P.Q. at 624. Claim 22, the court below found, like Claim 21, furnished particulars of Claim 20, adding the circumstance that the data passes from the "storage address generator" so as also to register simultaneously in the TIM memory. Put another way, the same data was being accumulated in the memory of each TIM as to that machine as well as in the central memory register. Judge Dooling found that Claim 22 really disclosed that the TIM memory and its immediately associated components are simply a conventional memory and unit adder used as a simple aggregator.

Claim 23, the "scratch" subsystem, is independent of Claim 20, and prevents betting on a "scratched" or withdrawn horse by using "a conventional equality comparator" to generate a "scratch signal" in the TIM and to prevent the TIM from operating to produce a ticket, "stepping" the "scan" to the next TIM. Put another way, a switch device emits a set of steady scratch signals and a comparison device matches those scratch signals with signals for attempted wagers on scratched entries, resulting in a rejection signal to the TIM. Judge Dooling found this not to go beyond "the obvious teaching of the use of a comparator" as a guard against taking wagers on scratches. As he said, a "comparator" exists to compare signals for identity or differences in a variety of ways, some of which can be gleaned from British Patent 749,836, cited by the Patent Office below.

Claim 24 was outlined by the patentee with reference to TIM scanning when no wagering transaction was being conducted at the TIM. Claim 24 and its dependent claim, Claim 25 (involving the converse situation where a transaction was being conducted or sought to be conducted) are the only ones of the claims in issue in which the plurality of TIMs is particularly significant to the claim. The object of the system is to provide a high-speed scanning means for interrogating a plurality of relatively slow operating TIMs. According to the patent itself, even absent a finding by the court below, the device which does the scanning the "scan counter" is a "chain of conventional cascaded binary counters," as discussed in Richards' Arthmetic Operations in Digital Computers, supra. The output of the scan counter is fed to the "scanner," which decodes the data from the scan counter and feeds it to the "interface" of the TIM. When depressed, the keys of the TIMs close switches, and when this is not done the scanner "steps" along to the next TIM or, if a key for a scratched or other wrong entry has been depressed, "the scratch circuitry" previously outlined (Claim 23) "steps" the scan to the next TIM. But when a wager has been processed and error-tested the depressed wager key is unlatched, and the bet ticket is printed and issued to the bettor. Judge Dooling found that the subsystem claim combined conventional components to perform a familiar assignment in a conventional way. Both the binary counter and the scanner themselves being conventional in data processing, the circuitry he found to be "pedestrian," with a very simple goal of furnishing a pulse tracking through a system and on completion to origin ticking a binary counter.

Dependent Claim 25, Judge Dooling found, added nothing, simply covering the alternative that a wager had been made. In that case, as we have said, there is no "step," and the "selected entry transaction" signal is simply processed. The claim covers delaying the stepping of the scan over the transacting TIM to the next TIM until the selected transaction signal is checked out or confirmed and permitted to proceed. Judge Dooling found this to be "detailed and uninspired circuitry doing the routine routinely," "not even approaching the versatility of (a prior patent known as) Schrimpf No. 3029414."

Claims 26 and 27 parallel Claim 23 in that their purpose is to constitute error checks incorporated in...

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