576 F.3d 1246 (Fed. Cir. 2009), 2007-1066, Hyatt v. Doll
|Citation:||576 F.3d 1246, 91 U.S.P.Q.2d 1865|
|Opinion Judge:||MICHEL, Chief Judge.|
|Party Name:||Gilbert P. HYATT, Plaintiff-Appellant, v. John J. DOLL, Acting Director, Patent and Trademark Office, Defendant-Appellee.|
|Attorney:||Kenneth C. Bass, III, Sterne, Kessler, Goldstein & Fox P.L.L.C., of Washington, DC, argued for plaintiff-appellant. On the brief were Wilma A. Lewis and Michael I. Coe, Crowell & Moring LLP, of Washington, DC. Of counsel on the brief was Gregory L. Roth, Law Offices of Gregory L. Roth, of La Palm...|
|Judge Panel:||Before MICHEL, Chief Judge, DYK and MOORE, Circuit Judges. Opinion for the court filed by Chief Judge MICHEL. Dissenting opinion filed by Circuit Judge MOORE. MOORE, Circuit Judge, dissenting.|
|Case Date:||August 11, 2009|
|Court:||United States Courts of Appeals, Court of Appeals for the Federal Circuit|
Plaintiff-Appellant Gilbert P. Hyatt appeals from the grant of summary judgment in favor of Jon Dudas, in his official capacity as the Director of the United States Patent and Trademark Office (" PTO" ),1 sustaining the decision of the
Board of Patent Appeals and Interferences (" Board" ) to uphold the examiner's rejection of 79 of the 117 claims of Hyatt's U.S. Patent Application Serial No. 08/471,702 (" the '702 application" ) as not supported by adequate written description. The appeal was argued on April 7, 2008. It is clear from the record that under our caselaw Hyatt had an affirmative and specific duty to disclose to the PTO the evidence excluded by the district court, and was so notified by the PTO, but willfully refused to cooperate in the examination process. On the facts of this case, we uphold the district court's exclusion of Hyatt's evidence. We therefore hold that the district court correctly granted summary judgment sustaining the Board decision because Hyatt offered no other evidence and the Board's decision was based on findings of fact and factual conclusions, all of which are supported by substantial evidence, and thus we affirm.
A. Proceedings Before the Examiner
Hyatt is the sole listed inventor on the '702 application. Hyatt has been registered as a patent agent since 1975 and prosecuted the application wholly on his own.2
The '702 application relates to computer and software technology and is entitled " Improved Memory Architecture Having a Multiple Buffer Output Arrangement." Hyatt filed the '702 application on June 6, 1995. J.A. 10001. The '702 application is a continuation or continuation-in-part of several earlier applications, some of which were themselves continuations or continuations-in-part. J.A. 10004. When first filed, the '702 application claimed priority back to 1984; Hyatt later amended the application to claim priority back to 1975. J.A. 10756-57.
The '702 application as originally filed had 15 claims, a 238-page specification, and 40 pages of drawings. J.A. 10000-293. It also incorporated by reference multiple publications (such as the " Texas Instruments, ALS/AS Logic Circuits Data Book, 1983" ), J.A. 10173-74, and a " disclosure document ha [ving] copies of many of" a list of referenced documents; on the list were manuals and specification sheets of products such as the " Viewpoint/3A Plus" and the " Siemens OEM Floppy Disk Drive FDD 100-8" . J.A. 10239-40. After several rounds of amendments to the specification and the claims, Hyatt ultimately cancelled all 15 original claims and added 117 new claims. J.A. 4. New claim 107 is not atypical:
A process of operating a memory system comprising the acts of:
generating input image information;
storing a two dimensional array of blocks of pixel image information by a two dimensional pixel block memory, the two dimensional array of blocks of pixel image information arranged in a two dimensional array of rows and columns of blocks of pixel image information,
wherein the blocks of pixel image information have boundaries there between;
generating write addresses and generating read addresses;
writing the two dimensional array of blocks of pixel image information into the two dimensional pixel block memory in response to the input image information and in response to the write addresses;
generating a first clock signal having a first clock rate;
accessing blocks of pixel image information in response to the read addresses, wherein the accessing of blocks of pixel image information from the two dimensional pixel block memory is at a first information rate in response to the first clock signal;
generating block boundary smoothing information to smooth the pixel image information at boundaries between blocks of pixel image information;
storing weight information by a weight memory;
generating accessed weight information by accessing the weight information stored by the weight memory;
generating smoothed weighted image information by weighting the pixel image information contained in the accessed blocks of pixel image information in response to the accessed weight information and in response to the block boundary smoothing information;
generating a second clock signal having a second clock rate that is different than the first clock rate of the first clock signal; and
generating output smoothed weighted image information in response to the smoothed weighted image information, wherein the generation of the output smoothed weighted image information is at a different information rate than the first information rate in response to the second clock signal.
In a January 7, 1997 office action, the examiner described Hyatt's final amendment as incomplete, stating:
Applicant also has failed to point out where in the specification support may be found for the amended and added claims. MPEP 714.02 states " Applicant should also specifically point out the support for any amendments made to the disclosure." The disclosure includes the claims.
Since the response appears to be bona fide, but through an apparent oversight or inadvertence failed to provide a complete response, applicant is required to complete the response within a TIME LIMIT of ONE MONTH from the date of this letter or within the time remaining in the response period of the last Office action, whichever is longer.
J.A. 10493. Hyatt responded a month later with further amendments to the specification and drawings J.A. 10498-503. and the following indication of where support for the 117 new claims and amendments to the specification could be found:
Representative antecedent basis includes page 23:2-19 for data compression; page 50:6-9 for the frame buffer; the section entitled " LOGIC BOARD" " Address Generators" at pages 117-127 for the address generator; the section entitled " MEMORY ARCHITECTURE" at pages 25-62 and the section entitled " MEMORY BOARDS" at pages 128-135 for the block memory having accessing, writing, and processing circuits; the section entitled " GRAPHICS PROCESSOR" at pages 9-14, the program listing at pages 214-30, and pages 29-31, 41, 42, 45, and 50 for the vector generator and processor; the section entitled " SPATIAL FILTERING" at
pages 15-24 and the program listing at pages 231-236 for the spatial processor; and pages 33:15-24:11 for the transform processor.
The Examiner is further referred to the Table of Contents (see the Preliminary Amendments) for additional antecedent basis.
In October 1997, the examiner issued a final office action rejecting all 117 of Hyatt's claims for lack of adequate written description, lack of enablement, double patenting, anticipation, or obviousness. J.A. 10634-64. The examiner rejected groups of claims for lack of written description and enablement based on the following thirteen limitations and groups of limitations:
• " a data decompressed video image input circuit generating data decompressed image information"
• " a writing circuit and an accessing circuit for writing and reading a block of video pixel image data into the block memory" and " the process of writing and reading a block of video pixel image data into the block memory"
• " a vector processor responsive to an accessed block of video pixel image information and to vector information"
• " a processor responsive to an accessed block of video pixel image information"
• " a spatial processor responsive to an accessed block of video pixel image information and to vector information and generating data compressed video"
• " a frequency domain processor," " generating frequency domain image information," and " frequency domain information"
• " a block processor responsive to an accessed block of pixel image information and to vector information"
• " [a]n input weight circuit generating input weight information," " an address generator which will generate weight addresses," " an address generator which will apply the weight addresses to the inputs of RAMS U5E and U6E at the same time the intensity bits are being applied to RAMS U3E and U4E," and " an address generator which will generate weight addresses for selecting weight values from the weight table to perform the desired weighting function at the spatial filter" (collectively, " the ‘ weight’ limitations" )
• " block boundary smoothing"
• " that the memory system is a video image data compression system"
• " a quantization weighting processor"
• " generating data compressed...
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