642 Fed.Appx. 1006 (Fed. Cir. 2016), 2015-1684, DSS Technology Management, Inc. v. Taiwan Semiconductor Mfg. Co.
|Citation:||642 Fed.Appx. 1006|
|Opinion Judge:||Taranto, Circuit Judge.|
|Party Name:||DSS TECHNOLOGY MANAGEMENT, INC., Plaintiff-Appellant v. TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NORTH AMERICA, SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA, INC., SAMSUNG TELECOMMUNICATIONS AMERICA, LLC, SAMSUNG SEMICONDUCTOR, INC., SAMSUNG AUSTIN SEMICONDUCTOR, L.L.C., Defendants-Appellees|
|Attorney:||CHRISTIAN JOHN HURT, Nix Patterson & Roach LLP, Irving, TX, argued for plaintiff-appellant. Also represented by DEREK TOD GILLILAND, Daingerfield, TX; WILLIAM ELLSWORTH DAVIS III, The Davis Firm, PC, Longview, TX. SCOTT A. CUNNING II, Haynes & Boone, LLP, Washington, DC, argued for defendants-app...|
|Judge Panel:||Before TARANTO, CLEVENGER, and HUGHES, Circuit Judges.|
|Case Date:||March 22, 2016|
|Court:||United States Courts of Appeals, Court of Appeals for the Federal Circuit|
This Disposition is Nonprecedential. (See Federal Rule of Appellate Procedure Rule 32.1)
Appeal from the United States District Court for the Eastern District of Texas in No. 2:14-cv-00199-RSP, Magistrate Judge Roy S. Payne.
CHRISTIAN JOHN HURT, Nix Patterson & Roach LLP, Irving, TX, argued for plaintiff-appellant. Also represented by DEREK TOD GILLILAND, Daingerfield, TX; WILLIAM ELLSWORTH DAVIS III, The Davis Firm, PC, Longview, TX.
SCOTT A. CUNNING II, Haynes & Boone, LLP, Washington, DC, argued for defendants-appellees Taiwan Semiconductor Manufacturing Company, Ltd., TSMC North America. Also represented by DAVID H. HARPER, DEBRA JANECE MCCOMAS, STEPHANIE SIVINSKI, Dallas, TX; KAREN S. PRECELLA, Fort Worth, TX.
JARED BOBROW, Weil, Gotshal & Manges LLP, Redwood Shores, CA, argued for defendants-appellees Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Telecommunications America, LLC, Samsung Semiconductor, Inc., Samsung Austin Semiconductor, L.L.C. Also represented by CHRISTOPHER MARANDO, Washington, DC; ALLEN FRANKLIN GARDNER, MICHAEL EDWIN JONES, Potter Minton PC, Tyler, TX.
Before TARANTO, CLEVENGER, and HUGHES, Circuit Judges.
Taranto, Circuit Judge.
DSS Technology Management, Inc. owns U.S. Patent No. 5,652,084, which describes and claims methods of making patterns in semiconductor wafers. DSS sued a number of companies, alleging that they manufacture products by using processes covered by claims 1-7 and 10 the '084 patent or sell products made by such processes. After the district court construed the claims, the parties stipulated to a judgment of noninfringement. DSS appeals the district court's construction of the term " patterned layer." DSS Tech. Mgmt., Inc. v. Taiwan Semiconductor Mfg. Co., No. 2:14-CV-199-RSP, 2015 WL 1737732, at *3-6 (E.D. Tex. Apr. 9, 2015). We affirm.
The '084 patent discloses a lithographic patterning process " to provide for a relatively reduced pitch for features of a patterned layer." '084 patent, col. 1, lines 40-41. In the description of the prior art, the '084 patent describes a typical lithography process: First, " photoresist is deposited over the layer to be patterned and is exposed to ultraviolet radiation through a mask that defines the pattern to be formed in the photoresist." Id., col. 1, lines 19-22. After irradiation, " [t]he photoresist is then developed to form a patterned photoresist layer over the underlying layer to be patterned. Those portions of the underlying layer that are not covered by photoresist may then be etched using suitable etch techniques and chemistries." Id., col. 1, lines 22-26. By such etching, " [t]he pattern in the photoresist is [ ] replicated in the underlying layer." Id., col. 1, lines 26-27.
According to the patent, however, the described conventional lithography methods " limit the size and density with which semiconductor devices may be fabricated." Id., col. 1, lines 28-30. The patent describes a purportedly novel two-stage process to enable smaller, denser fabrication. In the first stage, " a first imaging layer is formed over the semiconductor wafer," " [t]he first imaging layer is patterned in accordance with a first pattern to form a first patterned layer," and that " patterned layer is stabilized." Id., col. 1, lines 49-52. Then " [a] second imaging layer is formed over the first patterned layer such that the first patterned layer is surrounded by the second imaging layer. The second imaging layer is patterned in accordance with a second pattern to form a second patterned layer." Id., col. 1, lines 52-56. The result of the process is a " single patterned layer [ ] formed from the patterning of [the first] imaging layer . . . and the subsequent patterning of [the second] imaging layer." Id., col. 7, lines 38-40. The resulting (single, unified) patterned layer may then
" serve[ ] as a mask in patterning an underlying layer," so the pattern is " replicated in the underlying layer." Id., col. 12, lines 45-53.
Claim 1, the only independent claim at issue, states: 1. A lithography method for semiconductor fabrication using a semiconductor wafer, comprising the steps of:
(a) forming a first imaging layer over the semiconductor wafer;
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