Application of Nomiya

• Decision Date: 06 February 1975
• Docket Number: Patent Appeal No. 74-514.
• Citation: 509 F.2d 566
• Parties: Application of Kosei NOMIYA et al.
• Court: U.S. Court of Customs and Patent Appeals (CCPA)

509 F.2d 566

Application of Kosei NOMIYA et al.

Patent Appeal No. 74-514.

United States Court of Customs and Patent Appeals.

February 6, 1975.

Paul M. Craig, Jr., Washington, D. C., attorney of record, for appellants.

Joseph F. Nakamura, Washington, D. C., for the Commissioner of Patents; R. V. Lupo, Washington, D. C., of counsel.

Before MARKEY, Chief Judge, and RICH, BALDWIN, LANE and MILLER, Judges.

RICH, Judge.

This appeal is from the decision of the Patent Office¹ Board of Appeals affirming the rejection under 35 U.S.C. § 103 of claims 1-8 and 33 in application serial No. 768,794, filed October 18, 1968, for "Semiconductor Circuit Devices Using Insulated Gate-Type Field Effect Elements Having Protective Diodes." We reverse.

The Invention

Appellants' invention pertains to insulated-gate-type field-effect transistors (hereinafter IGFET) and their use in semiconductor capacitive memory circuits having very low capacitance. For ease of discussion we reproduce Figs. 1 and 2 of the application:

The structure of Q1 in Fig. 1 is an IGFET, consisting of two P-type² regions, S1 and D1, diffused into an N-type starting crystal, or substrate, usually of silicon, with an insulating oxide layer Si02 formed on the surface of the N-type substrate and contacting the diffused P-type regions. A metal gate electrode G1 is attached to the insulating layer. IGFETs used as switching devices, as contemplated by appellants, are customarily fabricated in the OFF-mode. In this mode, when no voltage is applied to the gate, the two P-type regions, called source (S1) and drain (D1), are electrically insulated from each other by the N-type region surrounding them. However, when a negative voltage, such as a clock pulse, is applied to the gate, the electric field so produced induces a thin P-type channel across the surface of the N-type channel across the surface of the N-type region connecting the source and the drain, permitting a current to pass between them. See In re Carlson, 412 F.2d 255, 56 CCPA 1309 (1969). Fig. 2 is a circuit diagram of a dynamic shift register employing the IGFET device of Fig. 1 as a switch to control a bit of information stored in capacitor C, which may be distributive capacitance of the circuit.

According to the application,

* * * since the gate G1 of an insulated gate-type field effect transistor Q1 as shown in Figure 1 has a high capacitive input impedance, a very small amount of electric charge accumulated on the gate G1 induces a high voltage and sometimes causes the insulating film (usually silicon dioxide) between the gate G1 and semiconductor substrate 1 to break down. Therefore, it has been proposed that a protective diode be formed, i. e. a zener diode Rec1, integrally in the semiconductor body 1 and that the diode be connected in parallel with the gate G1 as shown in Figure 1. It has been believed that the protective diode could prevent the insulating film from breakdown without interfering with the characteristics of the field effect transistor.

Appellants claim to have discovered that when IGFETs having protective diodes formed in the same substrate, as shown in Fig. 1, are used as switches for storing information or input signals in a memory element having very small capacitance (C on Fig. 2), parasitic transistor action between the protective diode and the drain region may take place when the PN junction JR of the protective diode Rec1 is forward biased³ by a noise signal, causing the signal stored in the memory element to discharge through the drain region D1 despite the lack of a pulse applied to the gate electrode. The solution to this problem found by appellants, which they claim as their invention, is a voltage-limiting means auxiliary to the protective diode, which can be a high resistance or another protective diode (hereinafter called "shunt diode"), formed outside the substrate or electrically isolated from other circuit elements on the substrate, connected in parallel with and in the same direction as the protective diode Rec1.

Claim 1, with reference letters keyed to Fig. 1 and emphasis supplied, is illustrative:

1. In a semiconductor device comprising:

an insulated gate-type field effect component Q1 including a semiconductor substrate 1 of first conductivity type, source S1 and drain D1 regions of second conductivity type opposite to said first conductivity formed in a surface of said semiconductor substrate, and an insulated gate electrode G1 disposed on said surface between said source and drain regions and insulated from said substrate by an insulating film Si02; and

a protecting semiconductor diode Rec1 formed integrally in said substrate and connected in parallel between said insulated gate electrode and said semiconductor substrate for protecting the insulating film interposed between said gate electrode and said substrate from breakdown; the improvement comprising

auxiliary means connected with said semiconductor device for preventing minority carriers from said protecting semiconductor diode from reaching said drain region through said semiconductor substrate when noise signals are applied to the protecting diode.

Claim 2 is similar to claim 1 and is cast in the same "Jepson" form. Dependent claims 3-8 depend from claim 2 and recite various added limitations. Claim 33 defines a "memory circuit device" containing appellants' invention. If claim 1 is patentable, so are the other claims.

The Rejection

The examiner cited Bergersen et al. Bergersen U.S. patent 3,408,511, issued October 29, 1968 on an application filed May 13, 1966. The Bergersen specification states in part:

This invention relates to an improved insulated-gate field-effect transistor (IGFET) circuit having large bi-polarity voltage capabilities. This circuit is operative as an active component of an electronic chopper or an electronic analog switching circuit and is adapted to receive large bipolarity analog input signal voltages.

When an insulated-gate field-effect transistor is used in analog switching or chopper circuits, it must be voltage controlled in such a manner that the P-N junctions between semiconductor substrate and source regions and between semiconductor substrate and drain regions do not become forward biased and enable current to flow from either the substrate region to the source region or from the substrate region to the drain region, respectively. This requirement means that the insulated-gate field-effect transistor can only handle input signals of a limited amplitude if these signals are connected directly in parallel with either of the above defined P-N junctions and between one of the source or drain regions and the substrate region, which is usually at ground potential. If, using the above-described connection, the input signals applied across either of the P-N junctions would be at a voltage level sufficiently high to forward bias these P-N junctions into conduction, then an alternative input signal connection must be resorted to. One such alternative connection involves disconnecting the substrate region from its ground return and from the source of input signals, leaving the substrate region floating. This mode of IGFET operation will prevent the P-N junctions between substrate and source regions and between substrate and drain regions from becoming forward biased, but it will also subject the substrate region to extraneous noise pickup and this is obviously an undesirable compromise for enabling the insulated-gate field-effect transistor to handle large bipolarity signals connected between either source or drain and substrate regions.

* * * * * *

A feature of this invention is the provision of an insulated-gate field-effect transistor circuit including adjacent source, substrate and drain regions with a P-N junction between the substrate and source regions and a P-N junction between the substrate and drain regions. A voltage limiting circuit is connected to the substrate region and includes a diode which is connected between the substrate region and either the source or the drain region. This diode becomes conductive for large amplitude signals of one polarity which are applied to one of the source or drain regions and thereby protects one of the above-identified P-N junctions from becoming forward biased. When large amplitude input signals of an opposite polarity are applied to the same source or drain region, this diode becomes reverse biased and prevents the input signals from reaching the other of the two P-N junctions, and forward biasing this junction.

* * * * * *

The substrate region * * * and the source and drain regions * * * are analogous to two spatially separated diodes connected back to back. Since the source and drain regions * * * are isolated by the substrate region * * * any drain to source current or source to drain current in the absence of a gate voltage is extremely low. The P-N junctions * * * of the so-called back to back diodes defined above must not be allowed to become forward biased for any amount of channel conduction since this would cause extraneous currents to flow to the input and output circuits of a practical chopping or switching device * * *.

It is significant that Bergersen does not explicitly disclose a protective diode formed in the same substrate as the IGFET so protected.

In order to understand one of appellants' arguments, we must look to the PTO position as it developed. In his first rejection of the appealed claims the examiner said:

Applicant's sic figures 1 and 2 reproduced supra illustrate the prior art. Bergersen et al teach the prevention of a diffused N region in a P substrate from being biased in the forward direction by the input signals through the use of a shunt diode and a resistor. Pursuant to this teaching it is obvious to one of ordinary skill in the art to prevent any of the diode junctions of Applicant's sic prior art figures from becoming forward bias sic through the use of a shunt diode. No new

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