EMI Group North America, Inc. v. Intel Corp.

• Decision Date: 29 September 1998
• Docket Number: 97-1153,Nos. 97-1137,s. 97-1137
• Citation: 157 F.3d 887,48 USPQ2d 1181
• Parties: EMI GROUP NORTH AMERICA, INC., Plaintiff-Appellant, v. INTEL CORPORATION, Defendant/Cross-Appellant.
• Court: U.S. Court of Appeals — Federal Circuit

Page 887

157 F.3d 887

48 U.S.P.Q.2d 1181

EMI GROUP NORTH AMERICA, INC., Plaintiff-Appellant, v. INTEL CORPORATION, Defendant/Cross-Appellant.

Nos. 97-1137, 97-1153.

United States Court of Appeals Federal Circuit.

Sept. 29, 1998.

Rehearing Denied; Suggestion for Rehearing In Banc

Declined Nov. 30, 1998. ^*

James P. Bradley, Sidley & Austin, of Dallas, Texas, argued for plaintiff-appellant. With him on the brief were Michael Chibib and Kathi A. Cover. Also on the brief were Ivan S. Kavrukov, Peter J. Phillips, Cooper & Dunham LLP, New York City; Donald F. Parsons, Jr., Morris, Nichols, Arsht & Tunnell, Wilmington, DE. Of counsel were D. Scott Hemingway, Sidley & Austin and Lisa B. Baeurle, Morris, Nichols, Arsht & Tunnel.

James J. Elacqua, Brobeck Phleger & Harrison, Palo Alto, CA, argued for defendant/cross-appellant. Of counsel on the brief were Susan K. Knoll, Jeffrey L. Garrett, and Michael S. Dowler, Arnold, White & Durkee, of Houston, TX. Also of counsel on the brief were Peter N. Detkin and Mark V. Seeley, Intel Corporation, of Santa Clara, CA. Of counsel was Amber L. Hatfield, Arnold, White & Durkee.

Before NEWMAN, PLAGER, and BRYSON, Circuit Judges.

PAULINE NEWMAN, Circuit Judge.

In this patent infringement case the United States District Court for the District of Delaware, following a two-day Markman hearing on the issue of "claim construction," granted summary judgment in favor of Intel Corporation, holding that three of Intel's manufacturing processes do not infringe United States Patent No. 4,486,943 (the '943 patent) owned by EMI Group North America. ¹ EMI appeals. Intel cross-appeals, inter alia, the ruling that Intel is not licensed under the '943 patent. We affirm the district court's judgment that the claims are not infringed, and dismiss the cross-appeal.

I THE PATENTED INVENTION

The '943 patent, entitled "Zero Drain Overlap and Self Aligned Contact Method for MOS Devices," issued December 11, 1984, is directed to a method of fabricating metal oxide semiconductor (MOS) field effect transistors, used in the integrated circuits of computer memory and microprocessor chips. Each MOS transistor acts as a switch to turn an electric current on and off. A chip may contain as many as several million transistors.

MOS transistors are built on a wafer or "substrate" that forms the bottom of the transistor. A MOS transistor typically consists of a gate electrode that has been deposited on a thin dielectric (insulating) layer over the substrate, with electrically conductive "source" and "drain" regions formed in the substrate on opposing sides of the gate electrode. These conductive regions are separated by the "channel," a poorly conductive region under the gate electrode. The basic MOS structure of the prior art is illustrated as follows:

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Upon application of voltage to the gate electrode, current flows from the source to the drain region, emitting an electrical signal that contributes to the operation of the chip. When the gate voltage is discontinued, the transistor reverts to static mode and ceases to emit signals.

Various methods of manufacturing MOS transistors have been described, whereby a semiconductor is produced by forming a thin layer of dielectric material (the oxide in the illustration) on a silicon substrate, then depositing gate electrode material such as polysilicon on the dielectric layer, "doping" the polysilicon with activating ionic substances so that it will conduct electricity, and vertically implanting or doping the source and drain regions of the silicon substrate with ions so that they become conductive. The portion of the substrate under the gate electrode is shielded from the vertical ion implantation, whereby after implantation the edges of the source and drain regions are generally vertically aligned with the sides of the gate electrode.

After implantation, the entire structure is heated to activate the ions in the implanted regions, as is necessary to make the regions conductive. This step leads to an undesirable consequence because during this heating process the implanted ions tend to diffuse through the substrate. Diffusion under the gate electrode causes buildup of an electric charge known as "Miller capacitance," which reduces the transistor's operating speed. The '943 patent is directed to a MOS transistor fabrication method that reduces the occurrence of Miller capacitance.

In accordance with the '943 method, dielectric oxide layers are thermally grown on the top and sides of the gate electrode. This oxide serves as a mask during the ion implantation of the substrate, thereby spacing the source and drain regions from the region under the gate, as shown in Fig. 1 of the '943 patent:

FIG. 1

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The dielectric oxide layers are differentially grown, meaning that the oxide (18) grown on the top and sides of the gate electrode (16) (POLY for polysilicon) is thicker than the oxide grown over the source and drain regions (20 and 22) of the substrate. The grown oxide on the top and sides of the gate electrode shields the gate electrode and the underlying portions of the substrate from ion implantation during creation of the source and drain regions, forming a gap that is free of implanted ions. Upon heat activation there is some migration of ions, but the conditions are controlled whereby there is substantially zero overlap in the vertical alignment of the gate electrode and the implanted source and drain regions. Since the ions do not migrate beyond the gap into the area underneath the gate electrode, Miller capacitance is avoided and operating speed is increased. Claim 1 of the '943 patent states the claimed process:

1. A method for fabricating on a substrate an MOS transistor having a gate electrode and a self-aligned source/drain region with zero overlap comprising:

(a) forming a doped polysilicon gate electrode upon but insulated from the substrate; then

(b) differentially thermally growing an oxide to serve as an implant mask having controlled thickness on both the top and sides of the gate electrode whereby a relatively thicker layer of oxide is developed on the top and sides of the gate electrode and a relatively thinner layer of oxide is developed on the intended source and drain regions of the substrate; then

(c) anisotropically etching said oxide;

(d) implanting a source/drain region in the substrate such that said implant mask shields an underlying portion of the substrate from implantation to result in a gap between a side edge of the gate electrode and a side edge of the implanted region; and then

(e) heat driving the implanted source/drain region until its side edge is substantially aligned with the previously separated side edge of the gate electrode, whereby the source/drain edge is aligned with the gate electrode edge and there is substantially zero overlap.

EMI charged that certain of Intel's MOS transistor fabrication methods infringe claim 1, literally or under the doctrine of equivalents.

INFRINGEMENT

Determination of infringement entails a two-step analysis wherein the claims are first construed by the court as a matter of law, following which the construed claims are applied to the accused device or method, a question of fact. Markman v. Westview Instruments, Inc., 52 F.3d 967, 976, 34 U.S.P.Q.2d 1321, 1326 (Fed.Cir.1995) (in banc), aff'd, 517 U.S. 370, 116 S.Ct. 1384, 134 L.Ed.2d 577, 38 U.S.P.Q.2d 1461 (1996). In Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1455, 46 U.S.P.Q.2d 1169, 1173 (Fed.Cir.1998) (in banc), the Federal Circuit confirmed that any disputed questions concerning the meaning and scope of patent claims, including the meaning of technologic and other terms ("the totality of claim construction") are treated as questions of law and are determined de novo on appeal, without deference to the decision of the trial court.

On appeal of the district court's grant of summary judgment we first must construe the claims, and then apply the rules governing summary judgment to the district court's rulings on the factual issues of infringement. When disputed questions of material fact underlie the summary judgment "the evidence of the nonmovant is to be believed, and all justifiable inferences are to be drawn in his favor." Anderson v. Liberty Lobby, Inc., 477 U.S. 242, 254, 106 S.Ct. 2505, 91 L.Ed.2d 202 (1986). The appellate tribunal must assure itself that there is no reasonable version of the facts, on the summary judgment record, whereby the nonmovant could prevail, recognizing that the purpose of summary judgment is not to deprive a litigant of a fair hearing, but to avoid an unnecessary trial. See id. at 250, 106 S.Ct. 2505. On this basis the grant of summary judgment is reviewed de novo on appeal. See, e.g., Stark v. Advanced Magnetics, Inc., 29 F.3d 1570, 1572-73, 31 U.S.P.Q.2d 1290, 1292 (Fed.Cir.1994).

The Markman Hearing

Construction of the claims by the trial court is often conducted upon a preliminary evidentiary hearing, called a Markman hearing in homage to the decision, cited supra, that established that this step must be performed by the judge, not the jury. This case illustrates the resolution of most of a complex infringement case with no more trial than a two-day Markman hearing.

At the Markman hearing the district court heard extensive testimony from the technical experts on the various issues and arguments concerning the scope of the claims in the context of the accused structures, and made findings thereon in construing the claims. The Federal Circuit has admonished that claims should preferably be interpreted without recourse to extrinsic evidence such as expert testimony, other than perhaps dictionaries or reference books, and that expert testimony should be received only for the purpose of educating the judge. See Markman, 52 F.3d at 983, 34 U.S.P.Q.2d at...