Inphi Corp. v. Netlist, Inc.

Decision Date13 November 2015
Docket NumberNo. 2015–1179.,2015–1179.
Citation116 U.S.P.Q.2d 2006,805 F.3d 1350
PartiesINPHI CORPORATION, Appellant v. NETLIST, INC., Appellee.
CourtU.S. Court of Appeals — Federal Circuit

David A. Jakopin, Pillsbury Winthrop Shaw Pittman LLP, Palo Alto, CA, argued for appellant. Also represented by Robert M. Fuhrer, McLean, VA.

Mehran Arjomand, Morrison & Foerster LLP, Los Angeles, CA, argued for appellee. Also represented by Bryan Leitch, Brian Robert Matsui, Washington, DC.

Before O'MALLEY, REYNA, and CHEN, Circuit Judges.

Opinion

O'Malley, Circuit Judge.

Netlist, Inc. (Netlist) is the assignee of U.S. Patent No. 7,532,537 (“the '537 patent”). Inphi Corporation (Inphi) filed a request for inter partes reexamination1 on June 9, 2010. The examiner rejected claims 1–9, 12–31, and 34–44 as obvious in view of the prior art. In order to overcome this rejection, Netlist amended its claims, narrowing them. Thereafter, the examiner withdrew its rejection of the claims and issued a final decision.

Inphi then filed a Notice of Appeal to the Patent Trial and Appeal Board (“PTAB” or “the Board”), alleging, among other things, that the amendment, which introduced a negative claim limitation, failed to satisfy the written description requirement of 35 U.S.C. § 112, paragraph 1 (2006).2 The Board issued a decision affirming the examiner's final decision declining to reject the relevant claims. Inphi Corp. v. Netlist, Inc., No. 2013–009066, 2014 WL 187535 (P.T.A.B. Jan. 16, 2014). Inphi filed a request for rehearing on February 18, 2014. The Board denied Inphi's request and affirmed its decision. Inphi Corp. v. Netlist, Inc., No. 2013–009066, 2014 WL 4180943 (P.T.A.B. Aug. 13, 2014) (“Board Decision ”). Inphi appeals from this decision. Because the Board's determination that the negative claim limitation met the requirements of § 112, paragraph 1 is supported by substantial evidence, we affirm.

Background

The '537 patent, entitled “Memory Module with a Circuit Providing Load Isolation and Memory Domain Translation” has an application date of January 19, 2006.3 The invention relates to computer system memory modules, which Netlist designs and manufactures. In particular, the invention improves the performance and/or capacity of the memory modules. '537 Patent, col. 1, ll. 29–32. Conventional computer systems, such as a desktop PC or a laptop, are compatible with modular memory systems. Users may simply insert a memory module into a slot or socket in the motherboard of their personal computer. The '537 patent concerns random access memory (“RAM”), which provides short-term storage of data for active software programs. Greater performance and/or capacity RAM leads, in general, to a better performing computer.

The memory module itself comprises a printed circuit board, on which memory devices (also known as memory chips) are mounted:

'537 Patent, Figure 16A. Figure 16A presents one side of a printed circuit board, 460. The memory devices—410, 420—of which there can be up to eighteen, are shown attached to the printed circuit board. The specification discloses multiple memory device types, including “random-access memory (RAM), dynamic random-access memory (DRAM), synchronous DRAM (SDRAM), and double-data-rate DRAM (e.g., SDR, DDR–1, DDR–2, DDR3).” Id. at col. 5, ll. 41–44.

The memory devices, therefore, can be of the Double Data Rate (“dDDR”) Synchronous Dynamic RAM (“SDRAM”) type. See id. at col. 36, 11. 28–31 (“In certain embodiments, the memory module 400 is a 1–GB unbuffered Double Data Rate (DDR) Synchronous Dynamic RAM (SDRAM) high-density dual in-line memory module (DIMM).”). At issue in this appeal is a negative claim limitation Netlist introduced by amendment, limiting the claimed chip selects to exclude three particular types of signals (CAS, RAS, and bank-address signals).4 Representative claim 1, as amended, is as follows:

1. A memory module comprising:
a plurality of memory devices, each memory device having a corresponding load; and
a circuit electrically coupled to the plurality of memory devices and configured to be electrically coupled to a memory controller of a computer system, the circuit selectively isolating one or more of the loads of the memory devices from the computer system, the circuit comprising logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip selects, and the physical memory domain is compatible with a second number of chip selects equal to twice the first number of chip selects, wherein the plurality of memory devices comprises double-data rate (DDR) dynamic random-access memory (DRAM) devices and the chip selects of the first and second number of chip selects are DDR chip selects that are not CAS, RAS, or bank address signals.

Joint Appendix (“J.A.”) 1366 (emphasis added). While the entire emphasized portion was added during reexamination, Inphi challenges only the underlined portion: “DDR chip selects that are not CAS, RAS, or bank address signals.” The examiner found the amendment sufficient to overcome its obviousness rejections. The Board affirmed the examiner's determination. Inphi contends, to the contrary, that the negative claim limitation added by amendment is not supported by the specification and thus constitutes impermissible new matter in violation of 35 U.S.C. § 112, paragraph 1.

Inphi requested rehearing of the Board's decision affirming the examiner. In its request, Inphi emphasized this court's decision in Santarus, Inc. v. Par Pharm., Inc., 694 F.3d 1344, 1351 (Fed.Cir.2012), which states that [n]egative claim limitations are adequately supported when the specification describes a reason to exclude the relevant limitation.” Inphi argued that [w]hile the Board gives lip service to the standard articulated in Santarus ... the Board also acknowledged that in this case there is no such reason expressly articulated in the specification.” J.A. 2241.

The Board explained in its decision on Inphi's request for rehearing that, “the '537 patent did not articulate expressly a reason to exclude RAS and CAS signals....” Board Decision, 2014 WL 4180943, at *1. The Board identified, however, three parts of the specification of the '537 patent upon which it relied in finding that the negative claim limitation was reasonably supported: (1) consistency with [Joint Electron Device Engineering Council (“JEDEC”) ] standards; (2) the '537 patent's excluding RAS and CAS signals in Table 2; and (3) various other passages from the '537 patent [including Figure 9A]....” Id.

The JEDEC is a global standard setting body for the microelectronics industry. The '537 patent incorporates by reference a JEDEC standards publication for DDR–1 memory devices, namely the JEDEC “Double Data Rate (DDR) SDRAM Specification,” published February 2004 (“JESD79D”). J.A. 1866–1948. The incorporation is provided in the description of Table 3A of the '537 patent : “Table 3A provides the numbers of rows and columns for DDR–1 memory devices, as specified by JEDEC standard JESD79D ... incorporated in its entirety by reference herein.” '537 Patent, col. 22, 11. 28–32. The JEDEC standard specifies that DDR signals (including CS, RAS, CAS, and bank address signals) are distinct from each other.

See J.A. 1882 (depicting Truth Table la, a logic table similar to Table 2 in the '537 patent ).

“Table 2 provides a logic table compatible with certain embodiments ... for the selection among ranks of memory devices [ ] using gated CAS signals.” '537 Patent, col. 18, 11. 25–27. Table 2 distinguishes among the relevant signals by providing separate columns for CS, RAS, and CAS.

Figure 9A, which the Board references in its discussion of “various other passages,” distinguishes chip select signals (CS0, CS1), command signals (understood to include CAS and RAS signals), and bank address signals (BA0–BAm) by displaying them on different signal lines in Figure 9A. As the patent describes, [t]he circuit 40 receives the two chip-select signals (CS0–CS1) and one row/column address signal (An+1) from the computer system. Both the circuit 40 and the register 230 receive the bank address signals (BA0–BAm) and at least one command signal (e.g., refresh, precharge, etc.) from the computer system.” '537 Patent, col. 17, ll. 2–7; see also id. at col. 16, ll. 62–66.

The Board found Inphi's challenges to the first two sources of evidence-the JEDEC standard and Table 2—“unpersuasive.” Board Decision, 2014 WL 4180943, at *1. In particular, the Board found that, [a]t a minimum, ordinarily skilled artisans would reasonably infer at least an implicit reason to exclude [RAS and CAS signals] based on their explicit exclusion in the context of [Table 2].” Id. Inphi's request for rehearing failed to address the “various other passages,” including Figure 9A. But in its decision, the Board relied on these “various other passages” that indicate that “chip selects are distinct from CAS, RAS, and bank address signals. Id. at *2.

Finally, the Board described the [p]atent owner's reference to JEDEC standards and [Inphi's expert's] unrebutted testimony that ordinarily skilled artisans would understand a DDR chip select to be exclusive of RAS, CAS, and bank address signals” as “bolster[ing] support for the negative limitation.” Id. at *2. Inphi appealed. We have jurisdiction under 28 U.S.C. § 1295(a)(4)(A).

Discussion

This court reviews legal conclusions of the PTAB de novo. In re Elsner, 381 F.3d 1125, 1127 (Fed.Cir.2004). We review factual findings of the Board for substantial evidence. In re Gartside, 203 F.3d 1305, 1316 (Fed.Cir.2000) ; Capon v. Eshhar, 418 F.3d 1349, 1351 (Fed.Cir.2005). This is a deferential standard of review. See In re Jolley, 308 F.3d 1317, 1320 (Fed.Cir.2002) (“If the evidence in record will support several reasonable but contradictory conclusions, we will not find the Board's decision unsupported by substantial evidence simply...

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