LG Electronics, Inc. v. Ati Technologies ULC

• Decision Date: 14 April 2016
• Docket Number: IPR2015-00325
• Parties: LG ELECTRONICS, INC., Petitioner, v. ATI TECHNOLOGIES ULC, Patent Owner. Patent 7, 742, 053 B2
• Court: Patent Trial and Appeal Board

LG ELECTRONICS, INC., Petitioner, v. ATI TECHNOLOGIES ULC, Patent Owner.

Patent 7, 742, 053 B2

No. IPR2015-00325

United States Patent and Trademark Office, Patent Trial and Appeal Board

April 14, 2016

Before JONI Y. CHANG, BRIAN J. McNAMARA, and RAMA G. ELLURU Administrative Patent Judges.

FINAL WRITTEN DECISION 35 U.S.C. § 318(A) AND 37 C.F.R. § 42.73

CHANG Administrative Patent Judge.

I. INTRODUCTION

LG Electronics, Inc. ("LG") filed a Petition requesting an inter partes review of claims 1, 2, and 5-7 ("the challenged claims") of U.S. Patent No. 7, 742, 053 B2 (Ex. 1001, "the'053 patent"). Paper 2 ("Pet."). Patent Owner, ATI Technologies ULC ("ATI"), filed a Preliminary Response. Paper 12 ("Prelim. Resp."). Upon consideration of the Petition and Preliminary Response, we instituted this trial as to claims 1, 2, and 5-7 of the '053 patent on June 15, 2015. Paper 13 ("Dec.").

Subsequent to institution, ATI filed a Patent Owner Response (Papers 21, 22, "PO Resp."); LG filed a Reply to the Patent Owner Response (Papers 33, 34, "Reply"); and ATI filed a sur-reply to LG's Reply with respect to the antedating issue (Papers 39, 40).^[1] An oral hearing was held on February 10, 2016.^[2]

We have jurisdiction under 35 U.S.C. § 6(c). This Final Written Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons discussed herein, and in view of the record in this trial, we determine that LG has shown by a preponderance of the evidence that claims 1, 2, and 5-7 of the '053 patent are unpatentable.

A. Related Matter

The '053 patent is asserted in Advanced Micro Devices, Inc. v. LG Electronics, Inc., No. 3:14-cv-0l012-SI (N.D. Cal.). Pet. 1.

B. The '053 Patent

The '053 patent discloses a computer system for multithreaded graphics processing. Ex. 1001, 2:36-41. The system includes a memory device for storing command threads and an arbiter for providing a command thread to a command processing engine, based on a priority scheme. Id. at 248-52, 3:29-35; see Paper 13, 2-3.

C. Illustrative Claim

Of the challenged claims, claims 1 and 5 are independent. Claim 2 depends from claim 1, and claims 6 and 7 depend directly from claim 5. Claim 5, reproduced below, is illustrative of the challenged claims.

5. A graphics processing system comprising:

at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads;

an arbiter, coupled to the at least one memory device, operable to select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads; and

a plurality of command processing engines, coupled to the arbiter, each operable to receive and process the command thread.

Ex. 1001, 8:4-15 (emphases added).

D. Prior Art Relied Upon

LG relies upon the following prior art references:

Lindholm

US 7, 015, 913 B1

Mar. 21, 2006

(Ex. 1004)

Stuttard

US 7, 363, 472 B2

Apr. 22, 2008

(Ex. 1005)

Moreton

US 7, 233, 335 B2

June 19, 2007

(Ex. 1006)

Whittaker

US 5, 968, 167

Oct. 19, 1999

(Ex. 1007)

Kimura

US 6, 105, 127

Aug. 15, 2000

(Ex.1008)

Admitted Prior Art - Figure 1, and the Background of the Invention Section of the '053 patent. Ex. 1001, 1:22-2:6, Fig. 1.

E. Instituted Grounds of Unpatentability

We instituted this trial based on the following grounds (Dec. 36-37):

Claims Basis References

5-7

§ 102(e)

Moreton

1 and 2

§ 103(a)

Moreton and Whittaker

1, 2, and 5-7

§ 103(a)

Lindholm in view of the Admitted Prior Art

1, 2, and 5-7

§ 103(a)

Stuttard in view of the Admitted Prior Art

II. ANALYSIS

A. Claim Construction

In an inter partes review, claim terms in an unexpired patent are given their broadest reasonable construction in light of the specification of the patent in which they appear. 37 C.F.R. § 42.100(b). Under the broadest reasonable interpretation standard, claim terms are given their ordinary and customary meaning as would be understood by one of ordinary skill in the art in the context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).

"command thread"

Each of independent claims 1 and 5 recites "at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads." Ex. 1001, 7:11-15, 8:5-8 (emphases added). Before institution, ATI urged us to construe "command thread" as "a sequence of commands." Prelim. Resp. 12-13. ATI also argued that a command thread does not encompass an instruction. Id. at 12.

In the Decision on Institution (Dec. 6-7), we noted that the word "command" is used in the Specification of the '053 patent consistent with its plain and ordinary meaning, as including an instruction. See, e.g., Ex. 1001, 4:21-27; Microsoft Computer Dictionary 111 (5th ed. 2002) (Ex. 3001) (defining "command" as an "instruction to a computer program that, when issued by the user, causes an action to be carried out"). Notably, the Specification discloses that "[u]pon the execution of the associated command of the command thread, the thread is thereupon returned to the station 302 or 304 at the same storage location with its status updated, once all possible sequential instructions have been executed." Ex. 1001, 4:21-27 (emphasis added). Dr. Nader Bagherzadeh testifies that, in the context of computer multithreading, a stream of instructions is called a thread. Ex. 1003 ¶¶ 23-24. This is consistent with the usage of the word "thread" in the prior art of record. See, e.g., Ex. 1005, 5:19-30. We further note that the plain meaning of "thread, " in the context of computer programming, means a process that is part of a larger process or program. Microsoft Computer Dictionary 518 (5th ed. 2002) (Ex. 3001). We, therefore, disagreed with ATI, in our Decision on Institution, that a command thread does not encompass an instruction, as it would be inconsistent with the term's plain and ordinary meaning. Rather-for purposes of the Decision on Institution-in light of the Specification, we construed the claim term "command thread" to encompass a stream of instructions or a process that is part of a larger process or program. Dec. 6-7.

After institution, ATI does not challenge our claim construction. PO Resp. 30. In fact, ATI's expert, Dr. Andrew Wolfe, testifies that one of ordinary skill in the art would have understood that the term "command thread" requires instructions. Ex. 2151 ¶¶ 57-58, 118. As such, we discern no reason to change our claim construction of "command thread" for this Final Written Decision.

"arbiter "

Each of independent claims 1 and 5 recites "an arbiter, coupled to the at least one memory device, operable to select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads." Ex. 1001, 7:16-19, 8:9-12.

In its Petition, LG proposes to construe the claim term "arbiter" as "any implementation of hardware and/or software that receives and provides a thread." Pet. 9. As support, LG cites to the Specification, which explains that an "arbiter may be any implementation of hardware, software or combination thereof such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine." Id. (citing Ex. 1001, 248-52).

Before institution, ATI argued that LG's proposed construction "ignores arbitration, " and proposed that the claim term "arbiter" should be construed as "a component for picking out a command thread among available pixel and vertex command threads." Prelim. Resp. 10-11. ATI's proposed construction, however, improperly would import other claim language-"picking out a command thread among available pixel and vertex command threads"-into the construction of the claim term "arbiter." Such a construction also would render other claim language superfluous-e.g., "select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads, " recited in claim 5. Moreover, the Specification explains that "arbiter 204 retrieves a command thread via connection 214 and provides the retrieved command thread to the command processing engine." Ex. 1001, 3:8-10 (emphasis added). As such, we declined to adopt ATI's proposed construction. Rather-for purposes of the Decision on Institution-in light of the Specification, we construed the claim term "arbiter" as any computer hardware, software, or combination thereof that receives and provides a command thread. Dec. 7-8. After institution, neither party proffers a different construction for this term. See PO Resp.; Reply. Upon review of this record, we discern no reason to change our claim construction of "arbiter" for this Final Written Decision.

"command processing engine "

Claim 5 recites cca plurality of command processing engines, coupled to the arbiter, each operable to receive and process the command thread." Ex. 1001, 8:13-15 (emphasis added). Claims 6 and 7 directly depend from claim 5, and further recite "wherein the plurality of command processing engines comprises at least one arithmetic logic unit" and "at least one texture processing engine" respectively. Id. at 8:16-21 (emphases added).

LG proposes to construe "command processing engine" as "any implementation of hardware and/or software that processes commands." Pet. 9. In its Patent Owner Response, ATI asserts that an ordinarily skilled artisan would have understood that the "command processing engine" limitation recited in claim 5 requires each command processing engine to be able to process both pixel and vertex command threads. PO Resp. 31; Ex. 2151 ¶ 125.

LG disagrees,...