Power Mosfet Technologies, L.L.C. v. Siemens Ag

• Citation: 378 F.3d 1396
• Decision Date: 17 August 2004
• Docket Number: No. 03-1469.,No. 03-1083.,No. 03-1470.,No. 03-1471.,03-1083.,03-1469.,03-1470.,03-1471.
• Parties: POWER MOSFET TECHNOLOGIES, L.L.C. and Third Dimension Semiconductor, Inc., Plaintiffs-Appellants, v. SIEMENS AG, Infineon Technologies Corporation, and Infineon Technologies AG, Defendants-Cross Appellants, and STMicroelectronics, N.V., STMicroelectronics, S.R.L, and STMicroelectronics, Inc. (formerly known as SGS-Thomson Microelectronics, Inc.), Defendants-Cross Appellants, and International Rectifier Corporation and International Rectifier Corporation North Carolina, Defendants-Cross Appellants.
• Court: United States Courts of Appeals. United States Court of Appeals for the Federal Circuit

378 F.3d 1396

POWER MOSFET TECHNOLOGIES, L.L.C. and Third Dimension Semiconductor, Inc., Plaintiffs-Appellants, v. SIEMENS AG, Infineon Technologies Corporation, and Infineon Technologies AG, Defendants-Cross Appellants, and STMicroelectronics, N.V., STMicroelectronics, S.R.L, and STMicroelectronics, Inc. (formerly known as SGS-Thomson Microelectronics, Inc.), Defendants-Cross Appellants, and International Rectifier Corporation and International Rectifier Corporation North Carolina, Defendants-Cross Appellants.

No. 03-1083.

No. 03-1469.

No. 03-1470.

No. 03-1471.

United States Court of Appeals, Federal Circuit.

Decided August 17, 2004.

Appeal from the United States District Court for the Eastern District of Texas, David Folsom, J.

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Allen M. Sokal, Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P., of Washington, DC, argued for plaintiffs-appellants. With him on the brief were Donald R. Dunner and Smith R. Brittingham IV. Of counsel on the brief was Alfonso Garcia Chan, Shore Deary, L.L.P., of Dallas, TX.

Robert Neuner, Baker Botts L.L.P., of New York, NY, argued for defendants-cross appellants Siemens AG, et al. With him on the brief were Neil P. Sirota of New York, NY; and Jeffrey D. Baxter, of Dallas, TX.

Constantine L. Trela, Jr., Sidley Austin Brown & Wood LLP, of Chicago, IL, argued for defendants-cross appellants STMicroelectronics, N.V., et al. With him on the brief was James P. Bradley, of Dallas, TX. Of counsel on the brief were Bruce S. Sostek and Jane Politz Brandt, Thompson & Knight LLP, of Dallas, TX. Of counsel was Li Chen, Sidley Austin Brown & Wood LLP, of Dallas, TX; and Max Ciccarelli, Thompson & Knight LLP, of Dallas, TX.

David E. Killough, Vinson & Elkins L.L.P., of Austin, TX, for defendants-cross appellants International Rectifier Corporation, et al. Of counsel was Glenn W. Trost, Coudert Brothers LLP, of Los Angeles, CA.

Before MICHEL, GAJARSA, and PROST, Circuit Judges.

GAJARSA, Circuit Judge.

Power Mosfet Technologies, L.L.C. ("PMT"), appeals the final judgment of the United States District Court for the Eastern District of Texas that United States Patent No. 5,216,275 (the "'275 patent") was not infringed by defendants-cross appellants Siemens AG, Infineon Technologies Corporation, and Infineon Technologies AG (collectively, "Infineon"), or by defendants-cross appellants STMicroelectronics, N.V., STMicroelectronics, S.R.L., and STMicroelectronics, Inc. (collectively, "ST"). Power Mosfet Techs. v. Siemens AG, No. 2:99-CV-168 (E.D.Tex. Sept. 30, 2002). PMT also appeals the district court's denial of its motion for a new trial. In the event that this court accepts certain arguments made by PMT, Infineon and ST conditionally cross-appeal the district court's judgment that the '275 patent was not anticipated by United States Patent No. 4,754,310 (the "Coe patent"). ST also conditionally cross-appeals the district court's judgment that the '275 patent is not anticipated by United States Patent No. 3,171,068 (the "Denkewalter patent"). Infineon alone cross-appeals the district court's denial of its motion for attorney fees. Finally, International Rectifier Corporation and International Rectifier Corporation North Carolina (collectively, "IR") cross-appeal the district court's denial of its motion for attorney fees under Federal Rule of Civil Procedure 54(d)(1) following the dismissal with prejudice of PMT's claims against it. For the reasons stated herein, we affirm the district court's judgment of noninfringement, its denial of PMT's motion for a new trial, and its denial of Infineon's motion for attorney fees and IR's motion for costs.

I. BACKGROUND

PMT is a Texas limited liability corporation with its corporate offices in Marshall, Texas, and is the owner of the '275 patent. The '275 patent is entitled "Semiconductor Power Devices with Alternating Conductivity Type High-Voltage Breakdown Regions."

A. Semiconductor Technology

Semiconductor power devices control the flow of electricity through an electronic circuit. They are typically constructed of silicon, which, by itself, is not a very good conductor of electricity. Silicon's conductivity, however, can be enhanced by a process known as doping. Doping adds impurities to the crystal structure of pure silicon and creates either a surplus or deficiency of free electrons in the silicon material. Both conditions enable the flow of current through the material. When doping results in a surplus of electrons, the material is described as "n-type" because it has a net negative charge. When the result is a deficiency of electrons (i.e., a surplus of "holes") the

NOTE: FIGURE 1 IS ELECTRONICALLY NON-TRANSFERABLE.

material is described as "p-type" because it has a net positive charge. Within the n-type and p-type categories, the material may be further categorized as heavily doped (n + or p + regions) or lightly doped (n - or p - regions).

The semiconductor power device described in the '275 patent is known as a MOSFET. A cross-section from a traditional MOSFET is reproduced above from figure 1 of the '275 patent. The '275 patent describes the fabrication process of the traditional MOSFET device as follows: an n - layer 5 is grown on an n + substrate 4, followed by the growth of a p + layer 3 on the top of the n - layer 5. The above-described process may also be performed with p-type materials substituted for the n-type materials, and n-type materials for the p-type. '275 patent, col. 5, ll. 23-29. In the traditional MOSFET design, layer 5 consists of a single conductivity type, either n- or p-type.

Also shown in figure 1 are the electrical connections of the semiconductor device. The terminals labeled "S" are the "source" terminals, where a positive voltage source is connected to the device. The terminal labeled "D" is the "drain" terminal, where the negative voltage connection is made. Terminal "G" is the "gate" terminal, and controls the current flow or, simply put, turns the device on and off. When on, current flows from the source to drain and, when off, current flow is blocked. The '275 patent refers to region 5 as the "voltage sustaining layer" because, when not conducting current, it sustains a voltage between the S and D terminals.

The on and off states of a MOSFET device are controlled by applying a voltage to the gate terminal. When applied, the gate voltage creates an electric field inside the device that manipulates the electrons in the doped silicon to create conducting channels for current through the silicon material. When the gate voltage is removed, the electrons return to their normal positions and the voltage sustaining layer again prevents current from flowing through the device.

Two characteristics of MOSFETs are relevant to understanding the invention disclosed by the '275 patent. The "on-resistance" ("Ron") of the device is the resistance of the conducting channel through the semiconductor material. The higher the on-resistance, the greater the power loss (and accompanying heat generation) resulting from the current flow through the device. The second characteristic is the "breakdown voltage" ("Vb"), which is the maximum voltage that the semiconductor device can sustain between its terminals. In traditional semiconductor devices, there is an exponential relationship between Vb and Ron. See'275 patent col. 1, ll. 29-31. Higher Vb values are a desirable characteristic in a semiconductor device, but the resulting benefit must be balanced against the corresponding undesirable increase in Ron values.

NOTE: FIGURE 4 IS ELECTRONICALLY NON-TRANSFERABLE.

The invention of the '275 patent is a design for a voltage sustaining layer that results in a new relationship between Vb and Ron. According to the ' 275 patent, the new relationship allows lower Ron values without the same magnitude of accompanying loss in Vb that results in traditional semiconductor devices. Id. at col. 1, ll. 55-66. Figure 4, reproduced from the '275 patent above, depicts a semiconductor device according to the invention. An n-type layer 5 is grown on an n + substrate 4. Layer 5 is then "trenched" to make deep U-grooves where the bottoms of the grooves "just reach [contact layer] 4." Id. at col. 5, l. 35. The trenches are then filled with p-material, resulting in alternating n-regions 6 and p-regions 7 that make up the voltage sustaining layer. Finally, a p + region 3 is grown over the alternating n- and p-regions. As with the traditional MOSFET devices, the ' 275 patent explains that p-type material can be substituted for n-type material, and vice versa.

The '275 patent designates its voltage sustaining layer the "composite buffer layer, or shortly, CB-layer," due to its alternating semiconductor regions. Id. at col. 1, ll. 57-58.

NOTE: FIGURES ARE ELECTRONICALLY NON-TRANSFERABLE.

The '275 patent further discloses several geometries for the differing conductivity areas, which are reproduced above. Independent claims 11 and 14 and dependent claims 12, 13, and 16 are at issue in this appeal. Claim 11 is representative,¹ and is set out below:

A semiconductor power device comprising:

a first contact layer of a first conductivity type;

a second contact layer of a second conductivity type; and

a voltage sustaining layer between said first and second contact layers,

said voltage sustaining layer comprising

first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type,

said first and second semiconductor regions being alternately arranged, the first contact layer contacting all said first semiconductor regions and said second semiconductor regions to form a first interface,

the second contact layer contacting with all the first and second semiconductor regions to form a second interface

wherein the first and second semiconductor regions are doped with dopants and the effective dopant distribution in every region in...