Techsearch, L.L.C. v. Intel Corp.

• Decision Date: 11 April 2002
• Docket Number: No. 00-1226.,00-1226.
• Citation: 286 F.3d 1360
• Parties: TECHSEARCH, L.L.C., Plaintiff-Appellant, v. INTEL CORPORATION, Defendant-Cross Appellant.
• Court: U.S. Court of Appeals — Federal Circuit

286 F.3d 1360

TECHSEARCH, L.L.C., Plaintiff-Appellant, v. INTEL CORPORATION, Defendant-Cross Appellant.

No. 00-1226.

United States Court of Appeals, Federal Circuit.

April 11, 2002.

Rehearing and Rehearing En Banc Denied June 4, 2002.^*

COPYRIGHT MATERIAL OMITTED

John C. Janka, Niro, Scavone, Haller & Niro, of Chicago, IL, argued for plaintiff-appellant. With him on the brief were Raymond P. Niro, and Robert P. Greenspoon. Of counsel was Joseph N. Hosteny.

Matthew D. Powers, Weil, Gotshal & Manges LLP, of Menlo Park, CA, argued for defendant-cross appellant. With him on the brief was Edward R. Reines. Of counsel were Josh A. Krevitt, and Elizabeth B. Honkonen.

Before NEWMAN, GAJARSA, and DYK, Circuit Judges.

Opinion for the court filed by Circuit Judge GAJARSA. Concurring opinion filed by Circuit Judge DYK.

GAJARSA, Circuit Judge.

This is a patent infringement case dealing with complex computer microprocessor technology. After extensive submissions by the parties and numerous preliminary findings by the United States District Court for the Northern District of California, the court issued summary judgment of noninfringement of TechSearch's U.S. Pat. No. 5,574,927 ("the '927 patent"), issued to Henry L. Scantlin, in favor of Intel Corp. ("Intel") and dismissed as moot Intel's counterclaim for declaratory relief. TechSearch, L.L.C. v. Intel Corp., No. 98-CV-03484, slip op. at 17-18 (N.D.Cal. January 31, 2000) (memorandum decision and order granting summary judgment) ("TechSearch Judgment"). TechSearch L.L.C. ("TechSearch") appeals from the grant of summary judgment. For the reasons discussed below, we affirm the judgment of the district court.

BACKGROUND

In the early 1990's, International Meta Systems, Inc. ("IMS") sought to develop a microprocessor known as the "IMS 3250" that could "emulate," or behave like, popular microprocessors such as the Intel 80X86 and the Motorola 680X0. On March 25, 1994, IMS filed a patent application encompassing the IMS 3250 processor. The application issued as the '927 patent on November 12, 1996. The inventor, Henry L. Scantlin, assigned all rights in the '927 patent to IMS, his employer.

The patent is entitled "RISC Architecture Computer Configured for Emulation of the Instruction Set of a Target Computer." The acronym RISC stands for "Reduced Instruction Set Computer." The patent discloses a RISC architecture computer microprocessor that can emulate the architectural behavior of another microprocessor. The claimed RISC processor and emulation technique permit use of existing software written for a target computer, even if that computer is a Complex Instruction Set Computer or "CISC" microprocessor, while retaining the benefits inherent in RISC processors. '927 patent, col. 2, ll. 52-57.

CISC architecture requires an extensive fixed set of, as the name suggests, complex instructions that are either hardwired or microprogrammed into the logic of a single microprocessor. '927 patent, col. 1, ll. 54-60. A RISC architecture design has certain design benefits compared to CISC microprocessor designs because a RISC architecture reduces the complexity of the chip through the use of microinstructions that perform a limited subfunction of a CISC instruction within a single clock cycle. '927 patent, col. 1, ll. 60-68. Thus, RISC architecture results in a microprocessor chip having fewer gates, using less power, and executing instructions significantly faster than a typical CISC microprocessor. '927 patent, col. 2, ll. 1-11.

Claims 1, 4 and 14 are the independent claims of the '927 patent, and read as follows:

1. A method for emulating the instruction set of a target computer on a RISC architecture computer, comprising the steps of:

1) fetching a target instruction of a format compatible with the instruction set of the target computer;

2) parsing and decoding said instruction into fields designating an opcode and operands;

3) converting said opcode into an address pointing to a sequence of one or more microcoded instructions 4) decoding said microcoded instruction into a LHS instruction having fields essentially compatible with a RISC architecture and a RHS instruction having fields to select a plurality of indirect registers pointing to emulated registers;

5) processing said emulated registers with an arithmetic logic unit;

6) calculating a condition code as a function of the operation of said arithmetic logic unit and a selection field within said microcoded instruction;

7) storing a result of said processing by said arithmetic logic unit;

8) storing a result of said condition code calculation; and

9) repeating steps 4-8 with a next microcoded instruction until an end of said microcoded sequence is encountered and then continuing at step 1 with a next target instruction.

'927 patent, col. 52, l. 64 to col. 53, l. 23.

4. A RISC architecture computer having a native instruction width of N bits configured for emulating target instructions from the instruction set of a target computer, comprising:

a plurality of emulation registers capable of corresponding to registers in the target computer and having data widths greater than or equal to the data widths of the registers in the target computer;

a plurality of indirect registers for selection of said emulation registers;

parsing means to extract a plurality of data fields from a target instruction, at least one said field[s] including an opcode;

dispatching means using said opcode to direct the RISC architecture computer to select at least one M + N bit expanded RISC instruction from a microcode memory;

an expanded instruction decoder for using said M bits from each said expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer, wherein said M bits define fields, said fields comprising a width field for designating the data width of said emulation registers and the data width of an arithmetic function, an indirect register field for designating said indirect registers, and a condition code field for designating a condition code emulation mode; and

condition code calculation means for determining the condition code for an arithmetic function according to said condition code field.

'927 patent, col. 53, ll. 33-61.

14. A RISC architecture computer having a native instruction width of N bits configured for emulating target instructions from the instruction set of a target computer, comprising:

a plurality of emulation registers capable of corresponding to registers in the target computer and having data widths greater than or equal to the data widths of the registers in the target computer;

a plurality of indirect registers for selection of said emulation registers;

parsing means to extract a plurality of data fields from a target instruction, at least one said field including an opcode dispatching means using said opcode to direct the RISC architecture computer to select at least one M + N bit expanded RISC instruction from a microcode memory;

an expanded instruction decoder for using said M bits from each said expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer; and

condition code calculation means for determining the condition code for an arithmetic function in accordance with the target computer.

'927 patent, col. 54, ll. 19-43.

As claimed, the invention includes a system or method for using a RISC architecture computer having a native instruction set including, inter alia, instructions of a width of N bits configured for emulating instructions from the instruction set of a target computer; a plurality of emulation registers for simulating registers of the target computer; a plurality of indirect registers for selecting the emulation registers; structure for extracting the data fields of a target instruction, including an opcode field; structure for using the opcode to direct the RISC architecture computer to select at least one M + N bit expanded RISC instruction from memory; an expanded instruction decoder for using M bits from the expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer; a condition code field for designating a condition code emulation mode; and structure for determining the condition code for an arithmetic function according to a condition code field.

Intel's x86 CISC microprocessors share instructions, adding new instructions to those which comprise the instruction set of the previously issued microprocessor. In other words, with the introduction of each new member of the Intel x86 family of microprocessors, new instructions are added to the CISC x86 instruction set of the previous version of the microprocessors. Thus, the P6 instruction set includes instructions unique to that version of the processors, as well as those used by the P5 microprocessor. Like the P6, the P5 instruction set includes all of the instructions found in the instruction set of the 486 microprocessor, as well as each additional instruction unique to the P5. Thus, each new processor executes all of the instructions of its predecessor, without modification, as well as the new instructions unique to that device.

After working on several versions of the 3250, IMS's attempts to produce the microprocessor commercially failed. TechSearch purchased the '927 patent as an asset in the IMS bankruptcy proceeding. Subsequently, TechSearch filed a complaint against Intel in September 1998 alleging that Intel's P6 line of microprocessors infringed the claims of the '927 patent.

The district court held a Markman hearing in August 1999 and issued a Memorandum Decision and Order on November 1, 1999. Recognizing that one skilled in the art would typically identify a computer as RISC- or CISC-based upon its published instructions rather than the microinstructions, the court concluded that, in the context of the patented invention, the classification of the microprocessor was properly...