Wiener v. NEC Electronics, Inc.

• Decision Date: 06 December 1996
• Docket Number: No. 96-1052,96-1052
• Citation: 41 USPQ2d 1023,102 F.3d 534
• Parties: Patricia WIENER, Plaintiff-Appellant, v. NEC ELECTRONICS, INC. and NEC Corporation, Defendants-Appellees.
• Court: U.S. Court of Appeals — Federal Circuit

Page 534

102 F.3d 534

41 U.S.P.Q.2d 1023

Patricia WIENER, Plaintiff-Appellant, v. NEC ELECTRONICS, INC. and NEC Corporation, Defendants-Appellees.

No. 96-1052.

United States Court of Appeals Federal Circuit.

Dec. 6, 1996.

Rehearing Denied Jan. 10, 1997.

Clarence E. Eriksen, Arnold, White & Durkee, Houston, TX, argued, for plaintiff-appellant. With him on the brief were Christopher R. Benson, Richard L. Stanley, and Timothy M. Honeycutt.

Charles D. Chalmers, Skjerven, Morrill, MacPherson, Franklin & Friel, San Jose, CA, argued, for defendants-appellees. With him on the brief were Justin T. Beck, and Scott D. Minden. Of counsel was Kimberly P. Zapata.

Before MICHEL, RADER, and SCHALL, Circuit Judges.

RADER, Circuit Judge.

Decision

Appellant, Patricia Wiener, appeals from a certified final judgment after the United States District Court for the Northern District of California granted summary judgment of non-infringement in favor of appellees, NEC Electronics, Inc. and NEC Corporation (collectively, NEC). Although the trial court improperly interpreted some claim terms, and improperly analyzed the issues of fact on marking, a proper claim interpretation still compels this court to affirm the grant of summary judgment of non-infringement and vacate the holding concerning marking.

Background

On November 6, 1973, U.S. Patent No. 3,771,145--entitled "Addressing an Integrated Circuit Read-Only Memory" (the '145 patent) issued to Patricia Wiener. The '145 patent discloses a means for addressing a memory array or matrix in a read-only memory (ROM) device. The patent recites a memory in the form of a matrix of columns and rows. At the intersection of each row and column the memory stores one unit of data called a bit. Each bit has a unique address specified by its corresponding row and column.

To retrieve the information from the memory array, a user first selects a particular row by applying an address input signal to the ROM. This signal identifies the row the user wishes to access. The user may then extract data from the selected row in eight-bit (byte) segments, each of which corresponds to eight columns of the seventy-two columns in the matrix. The claimed device includes a counter on the integrated circuit that enables the extraction of successive bytes (all seventy-two bits on the row, also known as words) from the columns with a single row addressing signal. The invention then routes these successive bytes into an output buffer for external use. This claimed counter provides two advantages. First, it allows extraction of data at an increased speed. Second, it allows the extraction to commence at any byte on the addressed row, not just from the first byte as in previous technologies.

Even though the '145 patent includes twenty-three claims, only four claims (9, 10, 12, and 13) are at issue in this appeal. Claim 9 states:

9. In a memory circuit on an integrated circuit chip having plural, individually addressable word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, a read-out circuit comprising:

first means on the chip for defining a data matrix having addressing rows and data columns, the intersection of a row and of a column defining a memory location;

second means on the chip responsive to a first, externally applied addressing code and connected for addressing one of the rows, pursuant to such addressing the content of the memory locations is available on the columns;

third means on the chip connected for sequentially calling on the columns for one byte at a time and providing bit value defining signals representing one respective byte for external extraction of the bytes as provided in particular sequence;

fourth means on the chip connected to the third means for establishing a particular beginning of a byte call sequence, and

fifth means on the chip for establishing a particular end for the byte call sequence.

Claim 10 depends from claim 9. Claim 12, the other independent claim at issue, reads:

12. In a memory on an integrated circuit chip having a plurality of word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, the combination comprising:

first means on the chip defining a data matrix that includes a plurality of columns of bit cells, each column of cells including a bit extraction column, one extraction column per bit position in a word location, the data matrix including a plurality of addressing rows, one row per word location and coupled to all columns of cells, one bit per column of cells;

second means on the chip defining a decoder network responsive to address bits applied externally to the chip, and having a plurality of outputs respectively coupled to the rows of the plurality, and including means to provide an addressing signal on one of the rows in response to a particular combination of applied address bits, so that the matrix applies the bits of the addressed location to the extraction columns and sustains the bits therein;

third means on the chip defining a counter progressing at a particular sequence thereby providing sequentially different enabling signals, while the data bits are sustained on said extraction columns;

fourth means connected to all of the extraction columns and to the third means and selecting the bits on some of the extraction columns in parallel and in response to one of the enabling signals from the counter, and providing a string of bytes in response to progression of the counter and of the enabling signals as provided by the counter; and

fifth means for presenting the bits of a byte concurrently and the bytes as sequentially provided by operation of the fourth means, as a byte string for use external to the chip.

Claim 13 depends from claim 12.

The alleged infringer, NEC, makes and sells memory chips called Video Random Access Memories (VRAMs). Like the patented invention, the accused devices are integrated circuit memories with data storage locations arranged in rows and columns. Further, the VRAM, again like the patented invention, stores a data bit at each row-column intersection. Data extraction in the VRAM commences by first addressing a row. At that point, however, the VRAM does not access the columns on the memory matrix byte-by-byte. Instead, a gate or latch closes or completes the circuit, which transfers the data on all columns within the selected row into an adjoining data register. The VRAM then disconnects the gates or latches to electrically isolate the data register from the memory array. The user then extracts data from the data register byte-by-byte. Simultaneously, new information is read into the columns of the memory array, in contrast to the '145 patent in which the data in the matrix is static.

This summary of the facts highlights the dispute over the meaning of claims 9 and 12. NEC asserts that its products have no mechanism to read data directly from the columns in the memory matrix, as allegedly required by the third means in claim 9 of the '145 patent. NEC contends that its VRAM does not call "on the columns for one byte at a time" as required by claim 9. NEC also asserts that its products have no mechanism on the chip to establish the particular beginning or end of a byte string extracted from a row of the memory matrix, as allegedly required by the fourth and fifth means of claim 9.

Conversely, Wiener asserts that the NEC products contain the third, fourth, and fifth means of claim 9. Specifically, Wiener contends a user extracts data from the data register that, according to Wiener, is part of the column of memory. Furthermore, Wiener argues that the NEC products contain mechanisms on the chip which establish the particular beginning and end of a byte string.

The dispute over the meaning of claim 12 is essentially identical to that concerning claim 9. Wiener contends that the proper interpretation of "extraction column" includes the data register latches and transfer gates between the data matrix and the read select circuits. NEC, on the other hand, urges an interpretation limiting the extraction columns to the area bounded by the data matrix.

After receiving recommendations from a special master, the district court considered these issues on cross-motions for summary judgment. The trial court granted NEC's motion for non-infringement and denied Wiener's motion for infringement. In reaching this result, the district court construed the terms "data column," "column," and "extraction column" to describe "only the passive elements, the adjacent P-zones, within the data matrix of the '145 patent." The district court then adopted the special master's finding:

The data in the Accused Products is transmitted from the memory matrix to the data register simultaneously, then read byte-by-byte from the data register, rather than from the data columns. Accordingly, the Accused Products lack any means for "sequentially calling on the columns for one byte at a time," and do not literally infringe claim 9....

....

The Accused Products do not meet the Third Means under the doctrine of equivalents.

Wiener v. NEC Elec., Inc., No. C 91-20843 JW, 1995 WL 429204, at * 5 (N.D.Cal. July 17, 1995). The district court also adopted a similar chain of special master findings in rejecting infringement under the fourth means of claim 9. Id. at * 5-6.

With respect to the fifth means of claim 9, the district court again adopted special master findings:

The Accused Products do not literally infringe the Fifth Means because the Accused Products contain no element on the chip for establishing an end to the byte string sequence....

[T]he Accused Products end the byte string sequence only by means external to the chip, and only internal means on the chip are claimed in the Fifth Means.

Id. at * 6. Thus, the district court rejected infringement under claim 9 of the '145 patent.

Similarly, the district court adopted findings rejecting infringement...