Bell Tel. Laboratories, Inc. v. Hughes Aircraft Co., Civ. A. No. 74-238.

• Decision Date: 19 July 1976
• Docket Number: Civ. A. No. 74-238.
• Citation: 422 F. Supp. 372
• Parties: BELL TELEPHONE LABORATORIES, INCORPORATED, Plaintiff, v. HUGHES AIRCRAFT COMPANY and General Instrument Corporation, Defendants.
• Court: U.S. District Court — District of Delaware

422 F. Supp. 372

BELL TELEPHONE LABORATORIES, INCORPORATED, Plaintiff, v. HUGHES AIRCRAFT COMPANY and General Instrument Corporation, Defendants.

Civ. A. No. 74-238.

United States District Court, D. Delaware.

July 19, 1976.

Richard F. Corroon, and Peter M. Siegloff, of Potter, Anderson & Corroon, Wilmington, Del. (Albert E. Fey, and Robert C. Morgan, of Fish & Neave, Edward Dreyfus, New York City, Peter V. D. Wilde, Murray Hill, N. J., of counsel), for plaintiff.

Thomas S. Lodge, of Connolly, Bove & Lodge, Wilmington, Del., Dugald S. McDougall, and Melvin M. Goldenberg, of McDougall, Hersh & Scott, Chicago, Ill. (Robert Thompson, Los Angeles, Cal., of counsel), for defendant Hughes Aircraft Co.

OPINION

CALEB M. WRIGHT, Senior District Judge.

Plaintiff, Bell Telephone Laboratories, Inc. ("BTL"), seeks relief under 35 U.S.C. § 291¹ against defendants Hughes Aircraft Co. ("Hughes") and General Instruments Corp. ("G.I."). BTL alleges that an interference exists between its United States Letters Patent Number 3,475,234 (the Kerwin patent), and United States Letters Patent Numbers 3,544,399 (the Dill patent) and 3,576,478 (the Watkins patent), owned by Hughes and G.I. respectively. BTL seeks an adjudication of that interference and a declaration that it is the sole owner of the patent rights in interference.

This Court has jurisdiction under 28 U.S.C. § 1338(a). Since plaintiff, BTL, is a New York corporation and both defendants are Delaware corporations venue is proper under 28 U.S.C. § 1391(c). Cf., Standard Oil Co. v. Montecatini Edison, S.p.A., 342 F.Supp. 124 (D.Del.1972).

Previously this Court has entertained a suit in which Hughes charged General Instruments with infringement of the Dill patent. General Instruments defended on the grounds, inter alia, that the Dill patent was invalid by reason of Watkins' prior invention. After separate trial on this priority issue, this Court held that although Watkins had conceived the invention in March of 1965, Watkins did not reduce the invention to practice until the filing of a patent application on November 17, 1966. Dill, however, was found to have conceived on May 1, 1966, and to have reduced to practice constructively by the filing of a patent application on October 26, 1966. Since Watkins was the first to conceive but the last to reduce to practice, his diligence from Dill's conception until his own filing was necessary to a finding that he was the prior inventor. No such diligence was found and Hughes prevailed. See Hughes Aircraft Co. v. General Instruments Corp., 374 F.Supp. 1166 (D.Del.1974). Before further proceedings on the remaining validity and infringement issues in that case occurred, the present suit was filed by BTL.

At an early stage in these proceedings, Hughes moved for dismissal on the ground that no interference existed. This Court was unwilling to hold on the record then extant that the patents were non-interfering. Accordingly that motion was denied. 185 U.S.P.Q. 660. G.I. participated in the briefing of that motion and urged that a three-way interference existed. However, as a result of a settlement agreement with Hughes, G.I. ceased participating in these proceedings prior to the argument on the Hughes' motion. See 185 U.S.P.Q. at 661.

Following denial of the dismissal motion, Hughes dropped its position that the Kerwin and Dill patents were non-interfering and the case proceeded to trial on the merits. The matter is now ready for decision.

The purpose of a suit under 35 U.S.C. § 291 is to establish priority of invention as between patentees. Priority is determined by the standard found in 35 U.S.C. § 102(g):

. . . In determining priority of invention, there shall be considered not only the respective dates of conception and reduction to practice of the invention, but also the reasonable diligence of one who was first to conceive and last to reduce to practice, from a time prior to conception by the other.

In the instant suit, the parties have stipulated to the Hughes dates determined by this Court in the Hughes v. General Instrument infringement action.² The parties therefore presented this Court with proofs only respecting BTL's dates of conception and reduction to practice. In the event that the Court were to determine that the Kerwin invention was conceived prior to May, 1966, and reduced to practice after October 26, 1966, BTL also sought to show that the Kerwin inventors exercised diligence from prior to May 1966 until such time as they had achieved a reduction to practice.³

The invention in the priority contest is directed to a semi-conductor device known as a "silicon-gate field effect transistor". ("S.G.F.E.T."). A field effect transistor ("F.E.T.") is a three-electrode electronic amplifier formed in a small semi-conductor. The semi-conductor is usually silicon and is referred to as a "slice", "chip", or "wafer". The three electrodes are known as the "source", "drain", and "gate". The source and the drain electrodes are formed in the silicon wafer by "doping" selected portions of the wafer with selected impurities. The area separating the source and drain is known as the "channel", and normally will resist the flow of current. However, in an F.E.T., the channel is overlayed with an insulating layer, and the gate electrode is formed on top of that layer. When an appropriate voltage is applied to this gate, current is able to flow along the previously resistant path between the source and drain. Further, variations in the voltage applied to the gate will result in variations in the current flowing between the source and drain.

Prior to the development of the invention in suit, a major problem in fabricating these devices was the positioning (or alignment) of the gate electrode. The devices are of very small dimensions and it was desirable to make them even smaller. It accordingly was very difficult to align precisely a strip of metal (usually aluminum) on top of the insulator which overlaid the channel separating the source and drain.

The S.G.F.E.T. avoided this alignment problem completely by virtue of its so-called "self-alignment" feature. To effect self-alignment, a silicon layer is positioned over the insulating layer covering the channel on the chip prior to forming the source and drain regions. The doping or diffusion step which results in formation of the source and drain is then performed. The silicon acts as a "mask" during this step and prevents doping of the channel region. The source and drain are thus formed precisely at the edges of the silicon gate, and the gate itself becomes sufficiently doped to become a conductor and thus act as an electrode.

This sequence, performing the diffusion step after placement of the gate electrode, had been impossible using the prior art, for the metal gates, usually aluminum, would melt at the temperatures required for diffusion.

The Work At Bell Telephone Laboratories.

Work on a S.G.F.E.T. by the Kerwin⁴ group can be traced to a meeting held at BTL in February, 1966. The meeting was called by Donald Klein, and was attended by members of his research group, as well as by other BTL technical personnel. Kerwin and Sarace were among those attending the meeting. (T-49, 278, 680).

The purpose of the meeting was to discuss problems which arose in making integrated circuits composed of large numbers of solid state devices. A significant problem respecting "yields" was always present in the manufacture of the circuits in a multi-step process. Even when each step in a process was highly efficient and resulted individually in a high yield, after a sequence of many such steps had been performed on a given device array, the percentage of operative devices in the array would be unsatisfactorily low. To overcome this problem, Klein hoped that his group would be able to come up with a so-called "go, no-go" sequence of device fabrication steps. A sequence of "go, no-go" process steps could approach 100% efficiency for it envisaged the use of materials which either would or would not be subject to reaction in a given chemical process step. (T-45-47; 49-50).

During the course of this meeting, at which a variety of potential process steps were discussed, Kerwin came to the key realization that placement of a thermally resistant gate prior to doping of the source and drain regions would eliminate the problems encountered in aligning the gate electrode. (T-280-85). Silicon, a material with which the group had experience, was the thermally resistant material chosen. (T-286). The S.G.F.E.T. fabrication process which resulted from this meeting was recorded by Klein (PX-10). Somewhat later, in early March, following discussion between Klein and his superior Hugh M. Cleveland, the latter developed a chart detailing the work assignments that would be involved in carrying out the project. (PX-15; T-576-77). In summary, the fabrication sequence involved the following steps:⁵

1. Preparation of a silicon chip. This step, while rather involved and time consuming, is only the preparation of starting materials. It does not relate directly to the invention.

2. Deposition of an insulating layer on the upper surface of the chip. The parties disagree on which insulating materials were initially embraced by the Kerwin group. Without question, silicon nitride was the insulator of choice by those at the February meeting. The contemporaneous evidence, however, convinces this Court that silicon nitride was not the only insulator considered. Reference to silicon nitride was somewhat equivocable, e. g., Klein's notes (PX-10) in reference to this insulating layer, contains the notation "(Si3N4?)" and Cleveland's notes (PX-15) expressly indicate that an alternative to silicon nitride was considered. This alternative insulator was a layer of silicon oxide over the silicon, followed by a layer of silicon nitride. This two layer insulating medium is referred to as a "sandwich". See Fig. 1, Appendix.

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