Spansion Inc. v. Petitioner

• Decision Date: 29 March 2011
• Docket Number: Nos. 2009-1461,Nos. 2009-1465,Nos. 2009-1460,Nos. 2009-1462,s. 2009-1460,s. 2009-1461,s. 2009-1462,s. 2009-1465
• Citation: 629 F.3d 1331,97 U.S.P.Q.2d 1417
• Parties: SPANSION, INC. and Spansion, LLC, Appellants, and Freescale Semiconductor, Inc., Appellant, and ATI Technologies, ULC, Appellant, and STMicroelectronics N.V., Appellant, and Qualcomm Incorporated, Appellant, v. INTERNATIONAL TRADE COMMISSION, Appellee, and Tessera, Inc., Intervenor.
• Court: U.S. Court of Appeals — Federal Circuit

629 F.3d 1331 97 U.S.P.Q.2d 1417 SPANSION, INC. and Spansion, LLC, Appellants, and Freescale Semiconductor, Inc., Appellant, and ATI Technologies, ULC, Appellant, and STMicroelectronics N.V., Appellant, and Qualcomm Incorporated, Appellant, v. INTERNATIONAL TRADE COMMISSION, Appellee, and Tessera, Inc., Intervenor. Nos. 2009-1460, 2009-1461, 2009-1462, 2009-1465. United States Court of Appeals, Federal Circuit. Dec. 21, 2010. Rehearing and Rehearing En Banc Denied March 29, 2011.

Carter G. Phillips, Sidley Austin LLP of Washington, DC, argued for all appellants. With him on the brief for STMicroelectronics N.V. were Eric A. Shumsky, Eric M. Solovy of Washington, DC; and Edward V. Anderson and Russell L. Johnson of San Francisco, CA. Of counsel was Ruthanne M. Deutsch of Washington, DC.

On the brief for Spansion, Inc., et al. were Paul D. Clement, Gilbert Kaplan, Daryl Joseffer and Dawn-Marie Bey King & Spalding Austin LLP of Washington, DC; and Ethan Horwitz of New York, NY. Of counsel was Charles Adams Pannell, III of Atlanta, GA.

Kenneth R. Adamo, Jones Day, of Cleveland, OH, for appellant Freescale Semiconductor, Inc. With him on the brief were Susan M. Gerber; and Blaney Harper and Lawrence D. Rosenberg of Washington, DC. Also on the brief for appellant ATI Technologies, ULC, were Michael J. Bettinger, Stephen M. Everett and Elaine Y. Chow, K & L Gates LLP, of San Francisco, CA.

Stephen B. Kinnaird, Paul, Hastings, Janofsky & Walker LLP of Washington, DC, for Qualcomm Incorporated. With him on the brief were Igor V. Timofeyev; Amy E. Simpson of San Diego, CA; Terrence P. McMahon, David H. Dolkas, and David L. Larson of Menlo Park, CA. Of counsel on the brief were Daniel R. Foster, McDermott Will & Emery LLP of Irvine, CA; Matthew J. Gryzlo of Chicago, IL; Margaret D. MacDonald, and Juliana M. Cofrancesco, Howrey LLP, of Washington, DC.

Megan M. Valentine, Attorney, Office of the General Counsel, United States International Trade Commission of Washington, DC, argued for appellee. With her on the brief were James M. Lyons, General Counsel, and Andrea C. Casson, Assistant General Counsel for Litigation.

Benjamin W. Hattenbach, Irell & Manella LLP of Los Angeles, CA, argued for Intervenor. With him on the brief were Morgan Chu, Jonathan H. Steinberg, Kenneth J. Weatherwax and Mark A. Kressel. Of counsel on the brief were Miguel A. Estrada and Wayne Barsky, Gibson, Dunn & Crutcher LLP of Washington, DC and Los Angeles, CA, respectively; and Amanda Tessar of Denver, CO.

Before LOURIE, FRIEDMAN, and LINN, Circuit Judges.

LINN, Circuit Judge.

Tessera, Inc. ("Tessera") filed a complaint with the United States InternationalTrade Commission ("the Commission" or "ITC") on April 17, 2007 under section 337 of the Tariff Act of 1930, 19 U.S.C. § 1337(a)(1)(B), alleging that seven respondents infringed U.S. Patents No. 5,852,326 (the "'326 patent") and No. 6,433,419 (the "'419 patent") through the importation or sale of certain semiconductor chips or products containing such chips. See In re Certain Semiconductor Chips with Minimized Chip Package Size and Products Containing Same, 72 Fed.Reg. 28521 (Int'l Trade Comm'n May 21, 2007). Tessera named as respondents Spansion, Inc. and Spansion, LLC (collectively, "Spansion"); Freescale Semiconductor, Inc. ("Freescale"); ATI Technologies, ULC ("ATI"); STMicroelectronics N.V. ("STMicro"); QUALCOMM, Inc. ("Qualcomm"); and Motorola, Inc. ("Motorola") (collectively, "Respondents"). Motorola subsequently settled its dispute with Tessera and was dismissed from the case. All other Respondents (collectively "Appellants") now appeal the Commission's final determination, ruling that Appellants directly infringe the asserted claims of the '326 patent and contributorily infringe the asserted claims of the '419 patent. In re Certain Semiconductor Chips With Minimized Chip Package Size and Products Containing Same, No. 337-TA-605, slip op. at 79, 2009 WL 1520119 (Int'l Trade Comm'n May 20, 2009) (Public Version) (" Final Determination "). Because the Commission's decision is supported by substantial evidence and is not contrary to law, this court affirms.

I. Background

A. Technology

The '326 and '419 patents, share a common specification and describe semiconductor chip packages. A semiconductor chip is a widely used miniaturized electronic circuit that has been manufactured in the surface of semiconductor material. A semiconductor chip package includes both the casing, which protects the chip, and the electrical connections (sometimes called "terminals" or "contact pads"), which allow the chip to be attached to a printed circuit board ("PCB"). The printed circuit board, in turn, can be connected to other components of an electrical device.

The present investigation relates to semiconductor packages containing face-up semiconductor chips in ball grid array assemblies. These are packages designed such that the side of the chip containing the electrical contacts (the "face" of the chip) faces away from a backing element (also referred to as a substrate, package substrate, or interposer) on which the chip is mounted via "die attach," which is the material used to mount the chip on the backing element.¹ The electrical contacts on the top of the chip are connected to the top side of the backing element by finewires called "leads." The bottom side of the backing element has terminals that are laid out in a grid pattern. These terminals are intended to be electrically attached to the contact pads on the printed circuit board using solder balls. An encapsulant encases the package to provide insulation and protection of the package components. Figure 2 depicts a sectional view of a face-up ball grid array chip package electrically attached to a PCB.

Image 1 (4.57" X 2.23") Available for Offline Print

As shown in Figure 2, chip 28 with electrical contacts 40 is mounted on a substrate (PCB) 20 with an interposer/package substrate 42 between the chip and the PCB. '326 patent col. 10 ll.23-67. The solder balls 52 bond each terminal 48 to the associated contact pad 24. Id. Each terminal 48 is also connected to one of the contacts 40 on chip 28 by a flexible lead 50. Id. Electrical devices generate heat during operation and subsequently cool when operation ceases. The electrical interconnections within the package (between the semiconductor chip and the backing element) and between the package and the printed circuit board are subjected to substantial strain resulting from expansion and contraction caused by these changes in temperature. Since the components are ordinarily formed by different materials having different coefficients of thermal expansion, the chip, the backing element, and the printed circuit board expand and contract by different amounts with each power cycle. This difference, called the differential thermal expansion, causes the electrical contacts on one component to move relative to the contacts of another component to which it is attached as the temperatures of the different components change. For instance, a semiconductor chip has a much lower coefficient of thermal expansion than either the backing element or the printed circuit board. During heating, the backing element beneath the chip tends to be constrained by the chip and expands much less than the board on which it is mounted, causing relative movement there between. This relative movement causes mechanical stress on the solder balls because the bottoms of the solder balls get pulled outward relative to the tops causing distortion. Repeated cycles of heating and cooling can ultimately lead to permanent damage to the solder balls and breakage of the electrical interconnections.

The patents at issue describe a semiconductor package with the ability to accommodate this relative movement between components by inserting a layer of compliantmaterial that is "flexible, compressible, and/or elastic" between the chip and its backing element. '326 patent col. 3 ll.61-64 ("Most preferably, a compliant layer is disposed between said terminals and said chip so that said compliant layer will be compressed upon movement of said terminals toward said chip."); see also In the Matter of Semiconductor Chips With Minimized Chip Package Size and Products Containing Same, Inv. No. 337-TA-605, slip op. at 42, 2008 WL 5098356 (Int'l Trade Comm'n Dec. 1, 2008) (Public Version) (" Initial Determination "). This compliant layer permits the terminals on the backing element to move relative to the chip inside the package offsetting some of the stress on the solder balls due to differential thermal expansion. The reduction of stress on the solder balls in turn decreases the occurrence of package failure and improves the reliability of the electrical devices containing such packages.

Tessera asserted claims 1, 2, 6, 12, 16-19, 21, 24-26, and 29 of the ' 326 patent and claims 1-11, 14, 15, 19, and 22-24 of the '419 patent against Respondents. Claim 1 of the '326 patent and claim 1 of the '419 patent are representative of the asserted claims and are set forth below with emphasis added to show limitations disputed in this appeal:

'326 patent:

1. A semiconductor assembly comprising:

a semiconductor chip having oppositely facing front and rear surfaces and edges extending between said front and rear surfaces, said chip further having contacts on a peripheral region of said front surface;

a backing element having electrically conductive terminals and lead portions thereon, wherein said lead portions are connected to said terminals, said backing element overlying said rear surface of said semiconductor chip such that at least some of said terminals overlie said rear surface of said chip:

bonding wires connected to said contacts on said front surface of said chip, said bonding wires extending downwardly alongside said edges of said chip and being connected to the lead portions on the backing element;

wherein said terminals are movable with respect to said chip.

'326...